High voltage pulser circuit for driving row-column conductor arrays of a gas discharge display capable of being made in integrated circuit form

ABSTRACT

There is disclosed an interfacing system for driving row-column conductor arrays to the gas discharge display panel in a low cost integrated circuit assembly. Due to the requirement of opposite polarity or bidirectional signals being applied to the conductors in the arrays, although the integrated circuits are functionally identical in translating low level logic signals to relatively high voltage (150 volts) pulse signals which are algebraically added to sustainer voltages, one of the circuits includes as a part of the logic circuit an inverting transistor; and to reduce current loading by the logic circuit on external data sources and at the same time serve as a part of a logic gate; and the high voltage switching circuits include a feedback diode for enhancing the response time.

United States Patent oBrien 1?. 1. 1

[541 HIGH VOLTAGE PULSER CIRCUIT 3,571,616 3/1971. Andrews ....;.....1...Q...i..... ....3o7/soo FOR DRIVINGROMCOLUMN 3,492,503 1/1971 Bose ....so7/2s4 A 3,149,239 9/1964 Wegang, "307/300 DISCHARGE DISPLAY CAPABLE OF BEING MADE IN INTEGRATED Primary Examiner-James W; Lawrence Assistant Examiner-Harold A. Dixon CIRCUIT FORM Ammey-aeverid e & De Grandi [72] Inventor: Thomas Edward O'Brien, Philadelphia, P [57] ABSTRACT [73] Assignee: Owens-Illinois,lnc, There is disclosed an interfacing'system ft: driving row-column conductor arrays to the gas disc arge dis- [22] Ffled' May 1971 play panel in a low cost integrated circuitassembly. [21] Appl. No.: 147,765 Due to the requirement of opposite polarity or bidirectional signals being applied to the conductors in the arrays,'.although the integrated circuits are func- [52] "307/241! 2 0 I tionally identical in translating low level logic signals 315/169 to relatively highvoltage (150 volts) pulse signals [51] III. C]. ..II03k 17/56 which areiaigebraicany added to sustainel. voltages [58] Freld of Search....307/24l, 255, 300, 315/169 R one of the circuits includes as a pan of the logic db cuit an inverting transistor; and to reduce current [56] References Clted loading by the logic circuit on external data sources and at the same as a Pan of a logic gate; and the high voltage switching circuits include a feed- 3,499,l67 3/1970 Baker ..3l3/220 back diode for enhancing the response time. 3,611,296 [0/1971 Johnson .....3l5/i69 3,614,467 10/1971 Tu ..3o7/21s 4 Claims, 1 Drawing Figure A Pcl 1%) I 1 I s Z 0T3 PNP TYPE I i EE 1 PC-S PC"! ca, ca; 04 PM 1 1 R4 1 W W COL MIA 680' ENABLE Zl HIGH VOLTAGE PULSER CIRCUIT FOR DRIVING ROW-COLUMN CONDUCTOR ARRAYS OF A GAS DISCHARGE DISPLAY CAPABLE OF BEING MADE IN INTEGRATED CIRCUIT FORM The present invention relates to new and improved circuitry for supplying discharge condition manipulating pulse potentials to the row-column conductor matrices of gas discharge display-memory panels of the type disclosed in Baker et al. U.S. Pat. No. 3,499,167 and British Patent Specification 1,161,832. It is an improvement on the circuits disclosed in Johnson U.S. Pat. application Ser. No. 888,743, now U.S. Pat. No. 3,611,296 and Johnson patent application Ser. No. 821,306, now U.S. Pat. No. 3,614,739. The gas compositions used in the panel shown in the Baker etal. patent have been greatly improved to now permit driving same by integrated circuits. In such gas discharge panels, the applied voltages are usually of two types, one, typically denoted as the sustainer voltage, is a periodic voltage which may be continuously or discontinuously applied but is typically of a sinusodial, square, triangular, etc., wave shape. This sustainer voltage must be applied commonly to all row and column conductors and, typically, one-half of the sustainer voltage is applied to one of the conductors of the array and the other half, 180 out of phase with respect to the former half, is applied to the other conductors of the array and, as in a preferred arrangement as disclosed in the aforementioned Johnson patent applications, are applied via the pulsing circuits which supply the other potentials referenced above. This second potential is a unidirectional voltage pulse, one-half applied to the row conductors and one-half of which is applied to the column conductors but of opposite polarity. Because of the relatively large numbers of panel lines to be driven, the circuitry for driving a row-column conductor array in the panels must be constructed at relatively low cost and high reliability. At the same time, it is highly desirable to provide logic circuitry in the integrated circuit environment or structure so as to reduce the number of wires or conductors to the panel. In this connection, the logic circuitry pulse as well as the arrangement of the circuits on the panels are known. It will be apparent that the circuitry disclosed herein need not be directly mounted on the panel but may be mounted on printed circuit boards and connected to the panel by flexible cables, conductors and the like.

Referring now to the drawing, which discloses a preferred embodiment of this invention, there is shown a gas discharge display/memory panel of the type disclosed in Baker et al. U.S. Pat. No. 3,499,167.

The panel is composed of a pair of glass plates and 11, plate 10 carrying conductor array 12 and plate 11 carrying column conductor array 13, respectively. The odd numbered conductors in the row conductor array 12 being served from one side of the panel whereas the even numbered conductors may be servied from the opposite side (not shown). In a similar fashion, column conductors 13 are carried on plate 11 and odd numbered or alternate ones of the column conductors C1, C3, C5 and C7 etc., are served from the upper plate extension, whereas the even numbered column conductors are served from circuitry on an opposite edge extension of plate 11 (not shown). It will be appreciated that all conductors may be served from the same side or in various other orientations or groupings not here pertinent.

The conductors within the active area of the panel have a dielectric charge storage coatings l5. and 16, respectively, and the plates are joined by a spacer sealant 17 to form a thin (under about 10 mils) discharge chamber 18 containing a gaseous discharge medium. The gas may be of a type and in the pressure range disclosed in Belgian US. Pat. No. 739,303 corresponding to Nolan application Ser. No. 764,577, filed Oct. 2, 1968.

Each of row conductors, R1, R3, R5, and R7, is served by an individual pulser PR1, PR3, PR5, and PR7, respectively, all of which are on one monolithic semiconductor body, and each of the column conductors C1, C3, C5, and C7, served by an individual column PCl, PCS, PCS, and PC9, respectively, which are on a monolithic semiconductor body of opposite conductivity type. As shown, each pulser is associated I with a gate circuit (to be described in greater detail hereinafter) each gate circuit requiring an enable pulse which is applied in common to the gate circuit in all pulsers in a sector on row enable bus 21 and a data input pulse as applied on data input terminals, row data 1, row data 3, row data 5, row data 7. Similarly, the column pulsers PCl, PCS, PCS, and PC7 are each equipped with logic circuitry driven by a pair of input pulses, one of which is the column enable pulse which activates column enable bus 22 and the column data terminals, column data terminal 1, column data terminal 3, column data terminal 5, column data 7. Thus, in order to activate any pulser circuit whether it be a column pulser or a row pulser requires two pulses, one specific to the pulser circuit per se as applied to the data terminals and one specific to a particular sector or area of the panel and designated as the enable pulse (row and/or column). It will be appreciated that more or less pulser chips may be controlled by a single enable pulse to row or column pulsers, respectively.

All of the pulser circuits require a low voltage (VLVl, VLV2) (no greater than approximately 12 volts) potential for operating the control or logic circuitry inputs and a relatively higher voltage (VHVI, VHV2) (approximately volts) for supplying high voltage pulses to be algebraically added to the sustainer voltages (of about the same magnitude). This direct current voltage is bidirectional in the sense that there is a corresponding negative voltage (VI-IV2) applied in common to all of the row pulser packages and having a common terminal. As shown there are four power supplies (VLVl, VLV2, VI-IVI, and VI'IV2). One set (VLVl, VI-lVl) supplies the column pulsers and one set (VLVZ, VI-IV2) supplies the row pulsers. These two sets are each floating on opposite phases (or sides) of the Sustaining Voltage (VS). It will also be noted that as in the case of the above-referenced Johnson patent applications, the sustainer voltages (Vs/2) are applied in series with the high direct current voltage and passes substantially unattenuated through the pulser circuits to the row and column conductors, respectively.

I-IIGI'I VOLTAGE PULSER CIRCUIT CONFIGURATIONS Referring now to circuit configuration PC-l, switching transistors Q3 and Q4 form a totem pole output stage driven by transistor 02. Transistor O1 is used as an active load and resistor R1 supplies current to transistor Q2 which in turn drives on switching transistor Q4, (Switching transistors Q3 and Q4 correspond to the output switching transistors of the above-referred Johnson patent applications and diode CR4 corresponds to diode D2, resistor R4 corresponds to resistor R3 of said "Johnson applications, so the switching action is essentially the same.)

Resistors R1 and R2 are used to split the current an are driven by the gate consisting of data diode CR1 and enable diode CR2. Current splitting is used to determine the amount of current coming out of transistor 02 which in turn drives on switching transistor Q4. Diode CR3 is a feedback diode, similar in action to'the well known Bakerclamp, and is used to drive the active load into a reduced conduction condition, to keep the switching transistor out of deep saturation. Output contact area OCA-l, in addition to having the sustainer potential thereat, will be pulsed to +VHV (+175 volts) less the small saturation drop in transistor Q4, and diode CR4 whenever transistor Q3 is rendered nonconductive.

' Each data input signal in conjunction with the signal voltage output of the enable circuitry (comprising resistor R5, transistor Q5, resistor R6 and phase inverter transistor O6), is used in a gating configuration formed by CR] and CR2 to allow transistor O2 to turn on which, in turn, turns on switching transistor Q4. The

ratio of resistor R1 to resistor R2 determines the current split which thereby reduces the impedance of transistor O1 in the "on condition. During the turnoff of transistor Q4, enough stored charge could exist on the base so the recombination time would increase the output turn-off delay. This has been improved by the use of feedback diode CR3 to greatly reduce the number of minority carriers and attendant recombination time. As indicated above, the mechanism is similar to a Baker clamp diode where the collector to base junction of transistor 04 is prevented from deep saturation by action of feedback CR3. The pulser circuitry for the row conductors, except for the observance of polarity considerations (NPN vs. PNP) is the same.

Enable circuitry for the row pulser circuits differs from that for the column pulser circuits in that on the row pulser circuits a single transistor 03 is used to transfer the enable signal. The high enable signal may have the same polarity for both pulser circuits (row and column) whereas all other polarities are opposite. For the column pulser circuits the enable signal turns off transistor Q which in conjunction with resistor R5 removes the drive current and thus shuts off current posite circuit in the row pulsercircuits. 0n the row pulser circuits, diodes CRS'and QE are used in conjunction to form a gate and function in the identical manner as diodes CR1 and CR2 on the column pulser circuits. Transistor QE is used to reduce the amount of current taken from the enable input when it is in the on-condition. As is known, in a dielectric isolation construction N-type wafers and P-type wafers are permitted, N-type wafers may have lateral PNP-transistors but the reverse is not desirable. This accounts for OE and associated PNPs being used on'the row conductor pu lser circuit chips and the opposite function not being used on the column conductor pulser circuit chips.

row and column conductors are identicalin converting or translating low level logic signals to high level volt ages and at the same time passing, in unaltered form, the sustaining voltage, because of the differences in conductivity types and the inherent differences in materials for fabricating such structures, the circuits are different. It is with respect to the specific high voltage transistor switching circuitry having its response time enhanced by a speed-up diode and an active transistor and in the unique combination of logic input enabling means that the invention is directed. It is with respect to the supplying of such potentials to a gas discharge display/memory panel of the type disclosed in the aforementioned Baker et al. patent as well-as other gas discharge panels a'ndcross' matrix display systems that the invention finds specific usefulness.

In the disclosed preferred embodiment, four'row conductor pulsers and their related input and output terminals, -voltage supply terminals and interconnecting conductors (as for example, the row enable" input contact terminal mama and conductor to each of the row enable transistors QE) are formed on a single chip and in like manner the column pulsers are formed on a single chip. However, in connection with the column feedback diode CR3 which is used to enhance the which functions as an active load on transistor 02 to provide a high speed drive thereto, transistor Q2 asan active element coupling the logic circuit to the switching transistor circuitry; transistor 05 u'sedas a drive for phase inverter transistor Q6 tocommonly control all diodes CR2 of the gate circuits inthe column pulsers, and transistor QE for the transferred logic enabling pulses, which thereby permit the same enabling pulses to be used for both kinds (row and column) of pulser circuits and, finally, resistors R1 and R2 are used to 'split or divide current the effect being active control of the impedance seen by the collector of transistorQ2.

What is claimed is:

1. In an electrical circuit system for supplying sustaining voltages and discharge manipulating pulse voltages to one group of row conductors and one group of column conductors in a gas discharge panel device to enter and remove information on said panel and in which transversely oriented row and column conductors effecting discharges in the gas have dielectric charge-storage means for charges produced on discharge interposed between said row and column conductors and the gas, at least a pair of monolithic semiconductor bodies, one for each said group of conductors and each processed to include a plurality of individual dielectrically isolated high voltage transistor switching circuits connected by conductors in circuit configurations described hereinafter including a plurality of contact areas to which connectionsto and from said circuit configurations are made, each said circuit configuration being functionally identical, wherein: each circuit configuration translates a low level input pulse signal voltage to a high level pulse l060ll 0588 signal voltage and feeds through a high level periodic signal voltage as said sustaining voltage, and means for supplying a 'low level input voltage constituting a source of said information to be entered on said panel,

the improvements wherein each of said high voltage transistor switching circuit includes diode feedback means between the collector of said high voltage switching transistor and said source of information signals for speeding the response of said switching transistor circuit, a further transistor element for each said circuit configuration, said further transistor element being operatively connected between said means for supplying a low level input voltage and said high voltage transistor switching circuit for each circuit configuration, respectively.

2. The invention defined in claim 1, said means supplying a low level input voltage is constituted by a multiple low voltage pulse signal input gate circuit, and one of said low voltage signal inputs is common to all said circuit configurations in a group for enabling same and wherein a further improvement comprises,

a transistor phase inverter circuit for receiving and inverting the phase of said common low voltage signal input, and

a current amplifier circuit for supplying an inverted current signal to said multiple input gate circuit as said common low voltage signal.

3. The invention defined in claim 1, said means sup- 6 plying a low level input voltage is constituted by a multiple low voltage pulse signal input gate. circuit and one of said low voltage signal inputs is common to all said circuit configurations in a group on a common semiconductor body, for enabling same'and wherein a further improvement comprises a transistor phase inverter circuit for inverting said common signal input voltage, there being one phase inverter for each said circuit configuration and each said phase inverter 'circuit being a part of said gate circuit.

4. The invention defined in claim 3 wherein .the

semiconductor bodies are of the opposite conductivity types, the further improvement wherein the other circuit configurations on the other of said semiconductor bodies include;

a further transistor phase inverter for receiving and inverting the phase of said common low voltage signal input, and

a current amplifier for supplying an inverted current signal to the multiple input gate circuit of each gate circuit, respectively, on said body as said common'low voltage signal, whereby the number of discharge points in said panel enabled by said common enable voltage is the product of the number of said row conductors in a group and the number of column conductors in a group.

" UNETED STATES ?ATENT GFFKE F V w.

'QERTIFICATE @F CGRRi'mQTiGN Patent No. 3,706,892 Dated December 19, 1972 Inventor) Thomas Edfiard O'Brien It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

COLUMN LINE "ERROR" SHOULD READ I l 53 New paragraph No paragraph beginning with Should be continuous sentence I! THE" 3 3 "referred" referenced Signed and sealed this 22nd day of May 1973.

(SEAL) Attes't:

jEDWARD M.FLETCHER,JR. ROBERT GOTTSCHALK Attesting Officer Commissioner of Patents 

1. In an electrical circuit system for supplying sustaining voltages and discharge manipulating pulse voltages to one group of row conductors and one group of column conductors in a gas discharge panel device to enter and remove information on said panel and in which transversely oriented row and column conductors effecting discharges in the gas have dielectric charge-storage means for charges produced on discharge interposed between said row and column conductors and the gas, at least a pair of monolithic semiconductor bodies, one for each said group of conductors and each processed to include a plurality of individual dielectrically isolated high voltage transistor switching circuits connected by conductors in circuit configurations described hereinafter including a plurality of contact areas to which connections to and from said circuit configurations are made, each said circuit configuration being functionally identical, wherein: each circuit configuration translates a low level input pulse signal voltage to a high level pulse signal voltage and feeds through a high level periodic signal voltage as said sustaining voltage, and means for supplying a low level input voltage constituting a source of said information to be entered on said panel, the improvements wherein each of said high voltage transistor switching circuit includes diode feedback means between the collector of said high voltage switching transistor and said source of information signals for speeding the response of said switching transistor circuit, a further transistor element for each said circuit configuration, said further transIstor element being operatively connected between said means for supplying a low level input voltage and said high voltage transistor switching circuit for each circuit configuration, respectively.
 2. The invention defined in claim 1, said means supplying a low level input voltage is constituted by a multiple low voltage pulse signal input gate circuit, and one of said low voltage signal inputs is common to all said circuit configurations in a group for enabling same and wherein a further improvement comprises, a transistor phase inverter circuit for receiving and inverting the phase of said common low voltage signal input, and a current amplifier circuit for supplying an inverted current signal to said multiple input gate circuit as said common low voltage signal.
 3. The invention defined in claim 1, said means supplying a low level input voltage is constituted by a multiple low voltage pulse signal input gate circuit and one of said low voltage signal inputs is common to all said circuit configurations in a group on a common semiconductor body, for enabling same and wherein a further improvement comprises a transistor phase inverter circuit for inverting said common signal input voltage, there being one phase inverter for each said circuit configuration and each said phase inverter circuit being a part of said gate circuit.
 4. The invention defined in claim 3 wherein the semiconductor bodies are of the opposite conductivity types, the further improvement wherein the other circuit configurations on the other of said semiconductor bodies include; a further transistor phase inverter for receiving and inverting the phase of said common low voltage signal input, and a current amplifier for supplying an inverted current signal to the multiple input gate circuit of each gate circuit, respectively, on said body as said common low voltage signal, whereby the number of discharge points in said panel enabled by said common enable voltage is the product of the number of said row conductors in a group and the number of column conductors in a group. 